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74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
April 1988 Revised October 2000
74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
General Description
The 74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O ports for bus-oriented applications. It features a preset capability for programmable operation, carry lookahead for easy cascading and a U/D input to control the direction of counting. All state changes, whether in counting or parallel loading, are initiated by the rising edge of the clock.
Features
s Multiplexed 3-STATE I/O ports s Built-in lookahead carry capability s Count frequency 100 MHz typical s Supply current 75 mA typical s Guaranteed 4000V minimum ESD protection
Ordering Code:
Order Number 74F579SC 74F579SJ 74F579PC Package Number M20B M20D N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" tot he ordering code.
Logic Symbol
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS009568
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74F579
Unit Loading/Fan Out
Pin Names I/O0-I/O7 PE U/D MR SR CEP CET CS OE CP TC Data Inputs or 3-STATE Outputs Parallel Enable Input (Active LOW) Up-Down Count Control Input Master Reset Input (Active LOW) Synchronous Reset Input (Active LOW) Count Enable Parallel Input (Active LOW) Count Enable Trickle Input (Active LOW) Chip Select Input Active (Active LOW) Output Enable Input (Active LOW) Clock Pulse Input (Active Rising Edge) Terminal Count Output (Active LOW) Description U.L. HIGH/LOW 3.5/0.333 75/15 0.25/0.333 0.25/0.333 0.25/0.333 0.25/0.333 0.25/0.333 0.25/0.333 0.25/0.333 0.25/0.333 0.25/0.333 25/12.5 Input IIH/IIL Output IOH/IOL 70 A/-0.2 mA
-3 mA/24 mA
5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA 5 A/-0.2 mA
-1 mA/5 mA
Function Table
MR X X X L H H H H H H SR X X X X L H H H H H CS H L L X X L PE X H H X X L CEP CET U/D X X X X X X H X L L X X X X X X X H L L X X X X X X X X H L OE X H L X X X X X X X CP X X X Function I/Oa to I/Oh in High Z (PE Disabled) I/Oa to I/Oh in High Z Flip-Flop Outputs Appear on I/O Lines Asynchronous Reset for all Flip-Flops Synchronous Reset for all Flip-Flops Parallel Load all Flip-Flops Hold Hold (TC Held HIGH) Count Up Count Down
(Not LL) (Not LL) (Not LL) (Not LL)
H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial = LOW to HIGH Clock Transition Not LL = CS and PE should never both be LOW voltage level at the same time.

X
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74F579
Logic Diagrams
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
VCC = Pin 16
GND = Pin 6
() = Pin Numbers
Detail A
3
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74F579
Absolute Maximum Ratings(Note 1)
Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Output in HIGH State (with VCC = 0V) Standard Output 3-STATE Output Current Applied to Output in LOW State (Max) ESD Last Passing Voltage (Min) twice the rated IOL (mA) 4000V
-65C to +150C -55C to +125C -55C to +150C -0.5V to +7.0V -0.5V to +7.0V -30 mA to +5.0 mA
Recommended Operating Conditions
Free Air Ambient Temperature Supply Voltage 0C to +70C
+4.5V to +5.5V
-0.5V to VCC -0.5V to +5.5V
Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol VIH VIL VCD VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage VOL IIH IBVI IBVIT ICEX VID IOD IZZ IIL IIH & IOZH IIL & IOZL IOS ICCH ICCL ICCZ Output LOW Voltage Input HIGH Current Input HIGH Current Breakdown Test Input HIGH Current Breakdown (I/O) Output HIGH Leakage Current Input Leakage Test Output Leakage Circuit Control Bus Drainage Test Input LOW Current Output Leakage Current Output Leakage Current Output Short-Circuit Current Power Supply Current Power Supply Current Power Supply Current -60 70 85 85 4.75 3.75 500 -0.2 70 -200 -150 110 120 125 10% VCC 5% VCC 10% VCC 5% VCC 2.4 2.7 0.5 0.5 5.0 7.0 0.5 50 Min 2.0 0.8 -1.2 Typ Max Units V V V V Min Min VCC Conditions Recognized as a HIGH Signal Recognized as a LOW Signal IIN = -18 mA IOH = -3 mA IOL = 20 mA (TC), IOL = 24 mA (I/On) IOL = 20 mA (TC), IOL = 24 mA (I/On) VIN = 2.7V (Non-I/O Pins) VIN = 7.0V (Non-I/O Pins) VIN = 5.5V (I/On) VOUT = VCC IID = 1.9 A All Other Pins Grounded VIOD = 150 mV All Other Pins Grounded VOUT = 5.25V VIN = 0.5V (Non-I/O Pins) VOUT = 2.7V (I/On) VOUT = 0.5V (I/On) VOUT = 0V VO = HIGH VO = LOW VO = HIGH Z
V A A mA A V A A mA A A mA mA mA mA
Min Max Max Max Max 0.0 0.0 0.0 Max Max Max Max Max Max Max
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74F579
AC Electrical Characteristics
TA = +25C Symbol Parameter Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL tPHL tPZH tPZL tPHZ tPLZ tPZH tPZL tPHZ tPLZ Maximum Clock Frequency Propagation Delay CP to I/On Propagation Delay CP to TC Propagation Delay U/D to TC Propagation Delay CEP or CET to TC Propagation Delay MR to I/On Propagation Delay MR to TC Output Enable Time CS or PE to I/O Output Disable Time CS or PE to I/O Output Enable Time OE to I/On Output Disable Time OE to I/On 70 3.0 5.0 5.0 5.0 4.5 4.5 2.5 3.5 5.0 6.5 3.0 5.5 2.0 2.0 3.0 5.0 2.0 2.0 VCC = +5.0V CL = 50 pF Typ 85 5.0 8.0 7.5 7.0 7.0 8.0 3.8 6.0 7.5 10.0 5.0 8.0 5.0 4.5 5.0 8.0 4.0 4.0 7.5 11.5 11.5 11.5 9.0 9.5 6.0 8.0 10.0 13.0 8.5 10.5 8.5 8.0 8.0 11.0 6.5 6.0 Max TA = 0C to +70C VCC = +5.0V CL = 50 pF Min 80 3.0 5.0 5.0 5.0 4.5 4.5 2.5 3.5 5.0 6.5 3.0 5.5 2.0 2.0 3.0 5.0 2.0 2.0 8.0 11.5 12.0 12.0 10.0 10.0 6.5 8.5 10.0 13.5 9.0 11.5 9.0 8.5 8.5 12.0 6.5 6.5 ns ns ns ns ns ns ns ns ns ns Max Units
AC Operating Requirements
TA = +25C Symbol Parameter Min tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tS(H) tS(L) tH(H) tH(L) tW(H) tW(L) tW(L) tREC Setup Time I/On to CP Hold Time I/On to CP Setup Time PE, CS or SR to CP Hold Time PE, CS or SR to CP Setup Time CET or CEP to CP Hold Time CET or CEP to CP Setup Time U/D to CP Hold Time U/D to CP Clock Pulse Width HIGH or LOW MR Pulse Width Recovery Time MR to CP 4.0 4.0 0.0 0.0 9.5 9.5 0.0 0.0 6.5 9.5 0.0 0.0 9.0 9.0 0.0 0.0 4.5 4.5 3.0 4.0 VCC = +5.0V Typ Max TA = 0C to +70C VCC = +5.0V Min 4.0 4.0 0.0 0.0 9.5 9.5 0.0 0.0 6.5 9.5 0.0 0.0 9.5 9.5 0.0 0.0 4.5 4.5 3.0 4.0 Max ns ns ns ns ns ns ns ns ns ns ns Units
5
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74F579
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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74F579
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M20D
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74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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